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PowerPC 405CR Embedded Controller Data Sheet
Features
* IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers - Supports JTAG for board level testing * PC-100 Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications * External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported * DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels * Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 10 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering - Programmable critical interrupt vector for faster vector processing * Two serial ports (16550 compatible UART) * One IIC (I2C) interface * General Purpose I/O (GPIO) available * Internal Processor Local Bus (PLB) runs at SDRAM interface frequency
Description
The IBM PowerPC 405CRTM is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while providing a base for custom chip designs. The controller is powered by a PPC405 embedded core. This core tightly couples a 266-MHz CPU, MMU, I- and D-cache, and debug logic. Fine-tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and greatly improves performance. The PPC405CR employs the IBM CoreConnectTM bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 100-MHz Processor Local Bus (PLB) and a 32-bit, 50-MHz On-Chip Peripheral Bus (OPB).High-performance peripherals attach to the PLB; and less performance-critical peripherals attach to the OPB. Technology: IBM CMOS SA12E 0.25 m (0.18 m Leff) Package: 27mm, 316-ball enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 0.9W, Maximum 2.0W
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While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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PowerPC 405CR Embedded Controller Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figures
PPC405CR Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 27mm, 316-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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PowerPC 405CR Embedded Controller Data Sheet
Tables
SysMem Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SysClk and MemClk Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O Specifications--All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 I/O Specifications--200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I/O Specifications--266MHz (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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PowerPC 405CR Embedded Controller Data Sheet
Ordering and PVR Information
Processor Frequency 200MHz 200MHz 266MHz 266MHz Rev Level B B B B
Product Name PPC405CR PPC405CR PPC405CR PPC405CR
Order Part Number1 IBM25PPC405CR-3BB200C IBM25PPC405CR-3BB200CZ IBM25PPC405CR-3BB266C IBM25PPC405CR-3BB266CZ
Package 27mm, 316 E-PBGA 27mm, 316 E-PBGA 27mm, 316 E-PBGA 27mm, 316 E-PBGA
PVR Value 0x40110041 0x40110041 0x40110041 0x40110041
JTAG ID 0x22051049 0x22051049 0x22051049 0x22051049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local IBM sales office. The part number contains a part modifier. This modifier provides for identification of future enhancements (for example, higher performance). Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PPC405CR User's Manual for details on the register content. IBM Part Number Key
IBM25PPC405CR-3BB200Cx
Shipping Package* IBM Part Number Grade 3 Reliability Package (E-PBGA) Case Temperature Range (-40C to +85C) Processor Speed Revision Level * Blank = Tray Z = Tape and reel
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PowerPC 405CR Embedded Controller Data Sheet
PPC405CR Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU PPC405 Processor Core JTAG 8KB D-Cache DCU Trace ICU 16KB I-Cache Arb On-chip Peripheral Bus (OPB) * See Peripheral Interface Clock Timings table GPIO IIC Power Mgmt DCRs *Serial Clock DCR Bus UART UART
DMA Controller (4-Channel)
OPB Bridge
Processor Local Bus (PLB) Code Decompression (CodePack)
SDRAM Controller 133MHz max - 13-bit addr - 32-bit data
External Bus Controller
External Bus Master Controller
66MHz max - 32-bit addr - 32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. Note: IBM CoreConnect busses provide: * 64-bit PLB interfaces up to 133MHz * 32-bit OPB interfaces up to 66MHz
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PowerPC 405CR Embedded Controller Data Sheet
Address Map Support
The PPC405CR incorporates two simple and separate address maps. The first is a fixed processor address map that serves the PowerPC family of processors. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCR). This address map is accessed by software running on the PPC405CR processor through the use of MTDCR and MFDCR commands.
SysMem Memory Address Map 4GB System Memory
Function Local Memory/Peripherals1 Reserved Total UART0 Reserved UART1 Reserved Internal Peripherals IIC0 Reserved OPB Arbiter Reserved GPIO Controller Registers Reserved Expansion ROM2 Boot ROM2 Sub Function Start Address 00000000 80000000 EF600000 EF600300 EF600308 EF600400 EF600408 EF600500 EF600520 EF600600 EF600640 EF600700 EF600780 F0000000 FFE00000 End Address 7FFFFFFF EF5FFFFF EFFFFFFF EF600307 EF6003FF EF600407 EF6004FF EF60051F EF6005FF EF60063F EF6006FF EF60077F EFFFFFFF FFDFFFFF FFFFFFFF 254MB 2MB 128B 64B 32B 8B 10MB 8B Size 2GB
Notes: 1. The Local Memory/Peripheral area of the memory map can be configured for SDRAM, ROM or Peripherals. 2. The Boot ROM and Expansion ROM area of the memory map are intended for use by ROM or Flash-type devices. While locating volatile SDRAM and SRAM in this region is supported by the controller it is not recommended that these regions be used for this purpose.
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PowerPC 405CR Embedded Controller Data Sheet
DCR Address Map 4KB Device Configuration Register
Function DCR Address Space1 Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Reserved Clock, Control and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved [0:3] = 0100 parm=0x0B0 parm=0x0B8 parm=0x0C0 [0:6] = 000110 0 [0:5] = 000100 [0:8] = 000001000 [0:8] = 000001001 [0:8] = 000001010 Base Address Strap/Parameter Start Address(0:9) 000 000 010 012 014 016 080 090 0A0 0A8 0B0 0B8 0C0 0D0 100 140 End Address(0:9) 3FF 00F 011 013 015 07F 08F 09F 0A7 0AF 0B7 0BF 0CF 0FF 13F 3FF Size 1KW (4KB)1 16W 2W 2W 2W 106W 16W 16W 8W 8W 8W 8W 16W 48W 64W 704W
Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
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PowerPC 405CR Embedded Controller Data Sheet
SDRAM Memory Controller
The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) * Memory bus operates at same frequency as PLB * 32-bit memory interface support * Programmable address compare for each bank of memory - 4GB of address space * Industry standard 168-pin DIMMS are supported (some configurations) * Up to 133MHz Memory, includes PC133 support * 4MB to 256MB per bank * Programmable address mapping and timing * Auto refresh * Page Mode Accesses with up to 4 open pages * Sync DRAM configuration via mode set command * Power Management (self-refresh) * Error Checking and Correction (ECC) support - Standard SEC/DED coverage - Aligned nibble error detect - Address error logging - Mixed ECC/non-ECC banks - Bypass mode
External Peripheral Bus Controller (EBC)
* Up to eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported * Up to 50MHz operation * Burst and non-burst devices * 8-, 16-, 32-bit byte-addressable data bus width support * Latch data on Ready, Synchronous or Asynchronous
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PowerPC 405CR Embedded Controller Data Sheet
* Programmable 2K clock time-out counter with disable for Ready * Programmable access timing per device - 256 Wait States for non-burst - 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS * Programmable address mapping * Peripheral Device pacing with external "Ready" * External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
DMA Controller
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/Gather capability for programming multiple DMA operations * 8-, 16-, 32-bit peripheral support (OPB and external) * 32-bit addressing * Address increment or decrement * Internal 32-byte data buffering capability * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses
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PowerPC 405CR Embedded Controller Data Sheet
UART
* One 8-pin UART and one 4-pin UART interface provided * Selectable internal or external serial clock to allow wide range of baud rates * Register compatibility with NS16550 register set * Complete status reporting capability * Transmitter and receiver are each buffered with16-byte FIFOs when in FIFO mode * Fully programmable serial-interface characteristics * Supports DMA using internal DMA engine
IIC Bus Interface
* Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers * Twelve memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocol * Programmable error recovery
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PowerPC 405CR Embedded Controller Data Sheet
General Purpose IO (GPIO) Controller
* Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. * All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Twenty-three GPIOs are multiplexed with: - 7 of 8 chip selects - All seven external interrupts - All nine instruction trace pins * Each GPIO output is separately programmable to emulate an open drain driver (i.e., drives to zero, threestated if output bit is 1).
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: * Supports 7 external and 10 internal interrupts * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to PPC405 processor core * Programmable critical interrupt priority ordering * Programmable critical interrupt vector for faster vector processing
JTAG
* IEEE 1149.1 Test Access Port * IBM RISCWatch Debugger support * JTAG Boundary Scan Description Language (BSDL)
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PowerPC 405CR Embedded Controller Data Sheet
27mm, 316-Ball E-PBGA Package
Top View
Gold Gate Release Corresponds to A1 Ball Location
Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded
15.0 TYP 27.0 REF 7.5 TYP
27.0
Note: All dimensions are in mm.
C 0.20 C
0.20
A 27.0 24.13
0.25 C 0.35 C
Bottom View
27.0
Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6
1.27 TYP Mold Compound Thermal Balls PCB Substrate
B
7 8
9
11 13 15 17 19 10 12 14 16 18 20
0.6 0.1 2.65 MAX
0.75 0.15 SOLDERBALL x 316 0.30 M C A B 0.15 M C
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically
Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOT0[TC0] EOT1[TC1] EOT2[TC2] EOT3[TC3] ExtAck ExtReq ExtReset Ball E20 J17 H18 L19 N17 P17 U19 P2 K17 J19 G20 C16 B17 B16 A14 A19 C15 B15 A8 U18 W14 Y10 U8 V19 F17 C19 V17 Y18 U14 V13 Y13 V12 W11 V11 G4 F2 W1 Y2 U5 Y3 P4 Power SDRAM Interface Interface Group Page 29 24
SDRAM Interface
24
External MASTER Peripheral Interface SDRAM Interface SDRAM Interface
26 24 24
External SLAVE Peripheral Interface
24
External SLAVE Peripheral Interface
24
SDRAM Interface
24
SDRAM Interface System Interface
24 28
SDRAM Interface
24
External SLAVE Peripheral Interface
24
External MASTER Peripheral Interface
26
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name Ball A1 A6 A10 A15 A20 B2 B19 C3 C18 D4 D17 E5 E10 E11 E16 F1 F20 J9 J10 J11 J12 K5 K9 K10 K11 K12 K16 K20 L1 L5 L9 L10 L11 L12 L16 M9 M10 M11 M12 R1 R20 Interface Group Page
GND
Power
29
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name Ball T5 T10 T11 T16 U4 U17 V3 V18 W2 W19 Y1 Y6 Y11 Y15 Y20 B18 D16 C17 P18 T17 W18 Y19 W13 V6 E19 T4 T3 V2 U15 W17 D18 C20 E18 D20 G17 F18 W20 Y7 W7 V8 U7 Y4 U6 W4 V5 W3 V4 U3 V1 T2 Interface Group Page
GND (cont)
Power
29
GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23] MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12
System Interface
28
System Interface External MASTER Peripheral Interface Internal Peripheral Interface Internal Peripheral Interface
28 26 26 26
Interrupts Interface
27
SDRAM Interface
24
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball H20 G18 J18 K19 L20 M20 M19 L18 L17 N20 N19 M18 M17 P20 P19 N18 U20 T18 W16 Y17 Y16 V14 Y14 U12 W12 Y12 Y9 W9 V10 U10 Y8 W8 V9 U9 F5 G5 P5 R5 T6 T7 T14 T15 F16 G16 P16 R16 E6 E7 E14 E15 SDRAM Interface Interface Group Page 24
SDRAM Interface Notes: 1. MemData0 is the most significant bit (msb) 2. MemData31 is the least significant bit (lsb)
24
OVDD
Power
29
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16] Ball A3 A4 B6 D7 C6 B7 D8 C7 B8 A7 D9 C8 B9 D10 C9 A9 B11 A11 B12 D11 A13 B13 C12 D12 B14 C13 D13 A16 C14 D14 A17 D15 E2 D3 D6 B5 C5 A5 B10 C10 A12 C11 Interface Group Page
External SLAVE Peripheral Interface Note: PerAddr0 is the most significant bit (msb) on this bus.
24
External SLAVE Peripheral Interface External MASTER Peripheral Interface
24 26
External SLAVE Peripheral Interface
24
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE RAS RcvrInh Ball U2 R4 U1 R2 R3 T1 N4 P3 N2 P1 M4 N3 M2 N1 L4 M3 L2 M1 K2 L3 K1 J1 J2 K3 K4 H1 H2 J3 J4 G1 G2 H3 B1 E4 C2 G3 E1 H4 E3 C1 D2 F4 F3 D1 C4 K18 E17 Interface Group Page
External SLAVE Peripheral Interface Note: PerData0 is the most significant bit (msb) on this bus.
24
External MASTER Peripheral Interface External SLAVE Peripheral Interface
26 24
External SLAVE Peripheral Interface
24
External SLAVE Peripheral Interface External SLAVE Peripheral Interface
24 24
External SLAVE Peripheral Interface
24
SDRAM Interface System Interface
24 28
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name Ball G19 J20 R17 T20 V16 H17 A18 D19 B4 A2 D5 F19 B20 B3 H19 W10 R18 U16 U13 V15 V20 T19 W15 V7 W6 W5 Y5 R19 E8 E9 E12 E13 H5 H16 J5 J16 M5 M16 N5 N16 T8 T9 T12 T13 U11 Other pins Note: G19 must be tied to OVDD or GND. All other reserved pins should be left unconnected. 29 Interface Group Page
Reserved
SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS TRST UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR[UART1_CTS] UART1_RTS[UART1_DTR] UART1_Rx UART1_Tx UARTSerClk
System Interface
28
JTAG Interface System Interface System Interface JTAG Interface JTAG Interface
27 28 28 27 27
Internal Peripheral Interface
26
Internal Peripheral Interface
26
Internal Peripheral Interface
26
VDD
Power
29
WE
SDRAM Interface
24
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PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal Name GND TDI PerAddr0 PerAddr1 PerCS3[GPIO12] Gnd PerAddr9 DMAReq3 PerAddr15 GND PerAddr17 PerCS6[GPIO15] PerAddr20 DMAAck3 GND PerAddr27 PerAddr30 SysErr DMAReq0 GND PerErr GND TMS TCK PerCS1[GPIO10] PerAddr2 PerAddr5 PerAddr8 PerAddr12 Ball B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Signal Name PerCS4[GPIO13] PerAddr16 PerAddr18 PerAddr21 PerAddr24 DMAReq2 DMAAck2 DMAAck1 GPIO1[TS1E] GND TmrClk PerR/W PerPar0 GND PerWE PerCS2[GPIO11] PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerCS5[GPIO14] PerCS7[GPIO16] PerAddr22 PerAddr25 PerAddr28 DMAReq1 DMAAck0 GPIO3[TS1O] GND Ball C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 Signal Name DrvrInh2 IRQ1[GPIO18] PerWBE3 PerWBE0 PerClk GND TDO PerCS0 PerAddr3 PerAddr6 PerAddr10 PerAddr13 PerAddr19 PerAddr23 PerAdd26 PerAddr29 PerAddr31 GPIO2[TS2E] GND IRQ0[GPIO17] SysReset IRQ3[GPIO20] PerPar2 PerBLast PerReady PerOE GND OVDD OVDD Ball E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G16 VDD VDD GND GND VDD VDD OVDD OVDD GND Rcrvinh IRQ2[GPIO19] SysHalt AVDD GND EOT1(TC1) PerWBE2 PerWBE1 OVDD OVDD DrvrInh1 IRQ5[GPIO22] TestEn GND PerData29 PerData30 PerPar1 EOT0[TC0] OVDD OVDD Signal Name
20
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment (Continued)
Ball G17 G18 G19 G20 H1 H2 H3 H4 H5 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J9 J10 J11 J12 J16 J17 J18 J19 J20 K1 Signal Name IRQ4[GPIO21] MemClkout1 Reserved ClkEn1 PerData25 PerData26 PerData31 PerPar3 VDD VDD SysClk BA1 TRST MemClkout0 PerData21 PerData22 PerData27 PerData28 VDD Thermal Ball Thermal Ball Thermal Ball Thermal Ball VDD BA0 MemData0 ClkEn0 Reserved PerData20 Ball K2 K3 K4 K5 K9 K10 K11 K12 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L9 L10 L11 L12 L16 L17 L18 L19 L20 M1 M2 Signal Name PerData18 PerData23 PerData24 GND Thermal Ball Thermal Ball Thermal Ball Thermal Ball GND CAS RAS MemData1 GND GND PerData16 PerData19 PerData14 GND Thermal Ball Thermal Ball Thermal Ball Thermal Ball GND MemData6 MemData5 BankSel0 MemData2 PerData17 PerData12 Ball M3 M4 M5 M9 M10 M11 M12 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P16 P17 Signal Name PerData15 PerData10 VDD Thermal Ball Thermal Ball Thermal Ball Thermal Ball VDD MemData10 MemData9 MemData4 MemData3 PerData13 PerData8 PerData11 PerData6 VDD VDD BankSel1 MemData13 MemData8 MemData7 PerData9 BusReq PerData7 ExtReset OVDD OVDD BankSel2 Ball P18 P19 P20 R1 R2 R3 R4 R5 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal Name GPIO4[TS2O] MemData12 MemData11 GND PerData3 PerData4 PerData1 OVDD OVDD Reserved UART0_DCD UARTSerClk GND PerData5 MemAddr12 HoldPri HoldAck GND OVDD OVDD VDD VDD GND GND VDD VDD OVDD OVDD GND
21
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment (Continued)
Ball T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name GPIO5 (TS3) MemData15 UART0_RX Reserved PerData2 PerData0 MemAddr10 GND ExtAck MemAddr5 MemAddr3 DQM3 MemData31 MemData27 WE MemData21 UART0_DTR ECC2 IIC_SCL UART0_DSR GND Ball U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name DQM0 BankSel3 MemData14 MemAddr11 HoldReq GND MemAddr9 MemAddr7 GPIO9[TrcClk] UART1_DSR [UART1_CTS] MemAddr2 MemData30 MemData26 ECC7 ECC5 ECC3 MemData19 UART0_RI Reserved ECC0 GND Ball V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Signal Name DQMfsCB UART0_RTS EOT2[TC2] GND MemAdd8 MemAdd6 UART1_RX UART1_RTS [UART1_DTR] MemAddr1 MemData29 MemData25 UART0_CTS ECC6 MemData22 GPIO8[TS6] DQM1 UART0_TX MemData1 IIC_SDA GPIO6[TS4] GND Ball W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name IRQ6[GPIO23] GND EOT3[TC3] ExtReq MemAddr4 UART1_TX GND MemAddr0 MemData28 MemData24 DQM2 GND MemData23 ECC4 MemData20 GND MemData14 MemData17 ECC1 GPIO7[TS5] GND
22
PowerPC 405CR Embedded Controller Data Sheet
Pin Lists
The PPC405CR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The following tables describe the package level pinout.
Pin Summary
Group
SDRAM External Peripheral External Master Internal Peripheral Interrupts JTAG System Total Signal Pins AVDD OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
No. of Pins
71 97 9 15 7 5 18 222 1 16 16 40 16 5 316
In the table "Signal Functional Description" on page 24, each I/O signal is listed along with a short description of the signal function. Some signals are multiplexed onto the same pin (ball) so that the pin is usable for different functions. Multiplexed signals are shown in square brackets following the default signal (for example, C0:3[BE0:3]) and described consecutively within each pin functional description. Active-low signals such as BE0:3 are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. These pins are described in the table using a single row with a text description that indicates the different functional uses of the pin. For example, the EBC peripheral controller address pins are used as outputs by the PPC405CR to broadcast an address to external slave devices when the PPC405CR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405CR. One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 39). Note that these are not multiplexed pins since the function of the pins is not programmable. The following table lists all of the I/O signals provided by the PPC405CR. Please refer to "Signals Listed Alphabetically" on page 13 for the pin number to which each signal is assigned.
23
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 1 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Description I/O Type
Notes
SDRAM Interface
Memory Data bus Notes: 1. MemData0 is the most significant bit (msb) 2. MemData31 is the least significant bit (lsb) Memory Address bus Bank Address supporting up to four internal banks Row Address Strobe Column Address Strobe DQM for byte lanes 0 (MemData0:7), 1 (MemData8:15), 2 (MemData16:23), and 3 (MemData24:31) DQM for ECC check bits ECC check bits 0:7 Select up to four external SDRAM banks Write Enable SDRAM Clock Enable Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData0:31
I/O
3.3V LVTTL
4
MemAddr12:0 BA0:1 RAS CAS
O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1
O I/O O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 4
External SLAVE Peripheral Interface
PerData0:31 Peripheral data bus used by PPC405CR when not in external master mode, otherwise used by external master Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405CR when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. Peripheral byte parity signals As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either peripheral controller or DMA controller depending upon the type of transfer involved. Used as inputs when external bus master owns the external interface Peripheral chip select bank 0 I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
PerAddr0:31
I/O
1
PerPar0:3
I/O
1
PerWBE0:3 PerWE
I/O
5V tolerant 3.3V LVTTL
1, 2
PerCS0
O
5V tolerant 3.3V LVTTL
2
24
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 2 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Description Seven additional peripheral chip selects or General Purpose I/O - To access this function, software must toggle a DCR register bit. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC405CR is the bus master, it enables the selected SDRAMs to drive the bus. Used by the PPC405CR when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC405CR when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405CR to indicate that data transfers have occurred. End Of Transfer/Terminal Count I/O Type 5V tolerant 3.3V LVTTL
Notes
PerCS1:7[GPIO10:16]
O[I/O]
1,2
PerOE
O
5V tolerant 3.3V LVTTL
2
PerR/W
I/O
5V tolerant
1, 2
PerReady
I
5V tolerant Rcvr 5V tolerant 3.3V LVTTL 5V tolerant Rcvr 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1, 2
PerBLast
I/O
1, 4
DMAReq0:3 DMAAck0:3 EOT0:3[TC0:3]
I O I/O
1, 5 6 1, 5
25
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 3 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Description I/O Type
Notes
External MASTER Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock to be used by an external master and by synchronous peripheral slaves Peripheral reset to be used by an external master and by synchronous peripheral slaves Hold Request, used by an external master to request ownership of the peripheral bus Hold Acknowledge, used by the PPC405CR to transfer ownership of peripheral bus to an external master ExtReq is used by an external master to indicate it is prepared to transfer data ExtAck is used by the PPC405CR to indicate that a data transfer occurred. Used by an external master to indicate the priority of a given transfer (0 = high, 1 = low) Used when the PPC405CR needs to regain control of peripheral interface from an external Master Used as an input used to record external Master errors and external slave peripheral errors O O I O I O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant Rcvr 5V tolerant 3.3V LVTTL 5V tolerant Rcvr 5V tolerant 3.3V LVTTL 5V tolerant Rcvr 5V tolerant 3.3V LVTTL 5V tolerant Rcvr 1, 5 1, 5 6 1, 4 6 1, 4
Internal Peripheral Interface
UARTSerClk Serial Clock used to provide an alternative clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0 Serial Data In UART0 Serial Data Out UART0 Data Carrier Detect UART0 Data Set Ready UART0 Clear To Send UART0 Data Terminal Ready UART0 Request To Send I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL Rcvr 1, 4
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS
I O I I I O O
1, 4 6 1, 4 1, 4 1, 4 6 6
UART0_RI
UART0 Ring Indicator
I
1, 4
26
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 4 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name UART1_Rx UART1 Serial In data Description I/O I Type 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL Rcvr
Notes
1, 4
UART1_Tx
UART1 Serial Out data. UART1 Data Set Ready or UART1 Clear To Send. To access this function, software must toggle a DCR register bit. UART1 Request To Send or UART1 Data Terminal Ready. To access this function, software must toggle a DCR register bit. IIC Serial Clock IIC Serial Data
O
6
UART1_DSR [UART1_CTS]
I
1, 4
UART1_RTS [UART1_DTR]
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
IICSCL IICSDA
I/O I/O
1, 2 1, 2
Interrupts Interface
Interrupt requests or General Purpose I/O. To access this function, software must toggle a DCR register bit.] 5V tolerant 3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
1, 5
JTAG Interface
TDI Test data in I 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL Rcvr 5V tolerant Rcvr 1, 4 1, 4
TMS
JTAG test mode select
I
1, 4
TDO
Test data out
O
TCK
JTAG test clock
I
TRST
JTAG reset
I
5
27
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 5 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Description I/O Type
Notes
System Interface
SysClk Main system clock input Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to start a system reset. The PPC405CR then holds the output low for 8192 cycles to reset all internal and external logic connected to SysReset. A system reset can also be initiated by software. Set to 1 when a Machine Check is generated. I 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL Rcvr 5V tolerant 3.3V LVTTL 1, 4
SysReset
I/O
1, 2
SysErr
O
Halt
Halt from external debugger. General Purpose I/O or Even Trace execution status.To access this function, software must toggle a DCR register bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR register bit. General Purpose I/O
I
GPIO1[TS1E] GPIO2[TS2E]
I/O[O]
1, 6
GPIO3[TS1O] GPIO4[TS2O]
I/O[O]
5V tolerant 3.3V LVTTL
1 (A22, AF18), 6 (AF18 only)
GPIO5:8[TS3:6]
Trace status. To access this function, software must toggle a DCR register bit. General Purpose I/O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR register bit. Test Enable Receiver Inhibit. Set to 1 for normal operation. Setting to 0 disables all inputs for test purposes. Driver Inhibit 1 and 2. Set to 1 for normal operation. Setting to 0 disables all outputs for test purposes. This input must toggle at a rate of less than one half the CPU core frequency (less than 100MHz in most cases). In most cases this input toggles much slower (in the 1MHz to 10MHz range).
I/O[O]
5V tolerant 3.3V LVTTL
1, 4
GPIO9[TrcClk]]
I/O[O]
5V tolerant 3.3V LVTTL
1, 4
TestEn RcvrInh DrvrInh1:2
I I I
5V tolerant Rcvr w/ PD 5V tolerant Rcvr 5V tolerant Rcvr 5V tolerant 3.3V LVTTL Rcvr
3 2 2
TmrClk
I
1, 4
28
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 6 of 6) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V, 10k to 5V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Description I/O Type
Notes
Power
GND AVDD OVDD VDD Ground Note: Pins J9-J12, K9-K12, L9-L12, and M9-M12 are also thermal balls. Filtered voltage input for PLL (analog) circuits Output driver voltage--3.3V Logic voltage--2.5V I I I I
Other pins
Reserved Ex cept for G19, do not connect signals, voltage, or ground to these pins. G19 must be tied to OVDD or GND.
29
PowerPC 405CR Embedded Controller Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Symbol VDD OVDD AVDD VIN VIN TSTG TC Value 0 to 0 to 2.71 3.61 Unit V V V V V C C
0 to 2.7 0 to 3.6 0 to 5.5 -55 to 150 -40 to +120
Notes: 1. If OVDD 0.4V it is required that VDD 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms duration during each power up or power down event.
Package Thermal Specifications
The PPC405CR is designed to operate within a case temperature range of -40C to 120C. Thermal resistance values for the E-PBGA package in a convection environment are as follows: Airflow ft/min (m/sec)
0 (0) Junction-to-case thermal resistance Case-to-ambient thermal resistance (without heat sink) Notes: 1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. 2. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. 3. TCMax = TJMax - PxJC, where TJMax is maximum junction temperature and P is power consumption. 4. The above assumes that the chip is mounted on a card with at least one signal and two power planes. 100 (0.51) 2 16 200 (1.02) 2 15 C/W C/W 2 18
Parameter
Symbol
Unit
JC CA
30
PowerPC 405CR Embedded Controller Data Sheet
Recommended DC Operating Conditions
Note: Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low Output Logic High Output Logic Low Input Leakage Current (No pull-up or pull-down) Input Leakage Current for PullDown Input Leakage Current for Pull-Up Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot (3.3V or 5.0V receivers) Output Max Allowable Overshoot (3.3V or 5.0V receivers) Output Max Allowable Undershoot (3.3V and 5.0V receivers) Case Temperature Symbol VDD OVDD AVDD VIH VIH VIL VOH VOL IIL1 IIL2 IIL3 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC Minimum 2.3 3.0 2.3 2.0 2.0 0 2.4 0 0 0 (LPDL) Typical 2.5 3.3 2.5 Maximum 2.7 3.6 2.7 OVDD 5.5 0.8 OVDD 0.4 0 400 (MPUL) 0 (MPUL) OVDD + 0.6 5.5 Unit V V V V V V V V Notes
A A A
V V V
-250 (LPDL)
- 0.6
OVDD + 0.3
V V
- 0.6 - 40
85
C
Capacitance
Parameter Input Capacitance Group 1 (3.3V LVTTL //O) Input Capacitance Group 2 (5V tolerant LVTTL I/O) Input Capacitance Group 3 Input Capacitance Group 1 (RX only pins) Symbol CIN1 CIN2 CIN3 CIN4 Maximum 2.5 3.5 5.0 0.75 Unit pF pF pF pF Notes
DC Electrical Characteristics
Parameter Active Operating Current (VDD) Active Operating Current (OVDD) PLL Voltage PLL VDD Input current Symbol IDD IODD VPLL IPLL 2.3 Minimum Typical TBD TBD 2.5 16 2.7 23 Maximum Unit mA mA V mA
31
PowerPC 405CR Embedded Controller Data Sheet
Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." AC specifications are characterized at VDD = 3.14V and TJ = 100C with the 50pF test load (CL) shown in the figure at right.
Output Pin CL = 50pf for all signals CL
SysClk and MemClk Timing
Symbol SysClk Input FC TC TCS TCH TCL MemClk Output FC TC FC TC TCH TCL MemClk clock output frequency--200MHz MemClk clock period--200MHz MemClk clock output frequency--266MHz MemClk clock period--266MHz Clock output high time Clock output low time 7.5 35% of nominal period 35% of nominal period 65% of nominal period 65% of nominal period 10 133 100 MHz ns MHz ns ns ns SysClk clock input frequency SysClk clock period Clock edge stability Clock input high time Clock input low time 25 15 - 40% of nominal period 40% of nominal period 66.6 40 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Parameter Min Max Units
Note: Input slew rate > 2V/ns
Timing Waveform
2.0V 1.5V 0.8V TCH TC TCL
32
PowerPC 405CR Embedded Controller Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405CR the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note 1). * Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the SDRAM MemClk since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the above requirements and does not adversely affect other aspects of the system.
33
PowerPC 405CR Embedded Controller Data Sheet
Peripheral Interface Clock Timings
Parameter PerClk output frequency--200MHz (for external master or synchronous slaves) PerClk period--200MHz PerClk output frequency--266MHz (for external master or synchronous slaves) PerClk period--266MHz PerClk output high time PerClk output low time UARTSerClk input frequency (Note 1) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency--200MHz TmrClk period--200MHz TmrClk input frequency--266MHz TmrClk period--266MHz TmrClk input high time TmrClk input low time Min - 20 - 15 50% of nominal period 33% of nominal period - 2TOPB+2 TOPB+1 TOPB+1 - 20 - 15 40% of nominal period 40% of nominal period Max 50 - 66 - 66% of nominal period 50% of nominal period 1000/(2TOPB+2ns) - - - 50 - 66 - 60% of nominal period 60% of nominal period Units MHz ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns ns ns
Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66MHz.for 266MHz parts.
34
PowerPC 405CR Embedded Controller Data Sheet
Input Setup and Hold Waveform
SysClk 1.5V TIS MIN Inputs 1.5V TIS MIN Data Bus D0:31 (Inputs)
TIH MIN
Valid TIH MIN
1.5V
Valid Valid
Output Delay and Float Timing Waveform
SysClk
1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
TOF
Outputs
1.5V
35
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications--All
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load na na na na Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS [UART1_DTR] UART1_DSR [UART1_CTS] UART1_Rx UART1_Tx UARTSerClk na na na na na na na na na na na na na na na na na na na na na na na na na na na na 19 19 12 12 12 12 12 12 12 12 12 n/a n/a 12 n/a 12 n/a n/a 12 n/a n/a dc dc n/a n/a n/a 12 12 8 8 8 8 8 8 8 8 8 n/a n/a 8 n/a 8 n/a n/a 8 n/a n/a n/a async async async async async
Interrupts Interface
IRQ0:6[GPIO17:23] JTAG Interface TCK TDI TDO TMS TRST
System Interface
DrvrInh1:2 GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt RcvrInh SysClk SysErr SysReset TestEn TmrClk
12
8
dc dc
dc dc
n/a n/a n/a n/a n/a n/a
n/a n/a n/a n/a n/a n/a
dc dc
dc dc
n/a n/a n/a 12 12 n/a n/a
n/a n/a n/a 8 8 n/a n/a
async
async async async async
36
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications--200MHz
Notes: 1. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1. 2. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and risingedge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission line circuit analysis. 3. SDRAM CLK0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a typical clock network or a lumped 10pF load. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load 7.3 5.8 7.3 4.7 6.2 6 6 7.8 0 6.2 7.4 7.4 8 n/a 9 10 8 9 10 8 10.5 8 n/a 8 8 8 n/a 8 8 n/a n/a 0.9 n/a 1 1 1 1 1 1 1 1 -1 1 1 1 0 n/a 0 0 0 0 0 0 0 0 n/a 0 0 0 n/a 0 0 n/a n/a 0.9 n/a Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
SDRAM Interface
BA0:1 BankSel0:3 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemClkOut0:1 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3[TC0:3] PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr n/a n/a n/a n/a n/a n/a 2 n/a n/a 2 n/a n/a n/a dc dc 4 4 n/a 6 n/a 4 5 9 4 n/a n/a 6 n/a n/a 4 6 n/a 4 n/a n/a n/a n/a n/a n/a 1 n/a n/a 1 n/a n/a n/a dc dc 1 1 n/a 1 n/a 1 1 1 1 n/a n/a 1 n/a n/a 1 1 n/a 1 19 19 19 40 19 19 19 19 19 19 19 19 12 n/a 12 19 12 12 19 12 19 12 n/a 12 12 12 n/a 19 12 n/a n/a 19 n/a 12 12 12 25 12 12 12 12 12 12 12 12 8 n/a 8 12 8 8 12 8 12 8 n/a 8 8 8 n/a 12 8 n/a n/a 12 n/a SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 1, 2 2 1, 2 2 2 2 2 1, 2 2, 3 2 1, 2 1, 2
External SLAVE Peripheral Interface
External MASTER Peripheral Interface
4
37
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications--266MHz (Preliminary)
Notes: 1. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1. 2. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and risingedge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission line circuit analysis. 3. SDRAM CLK0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a typical clock network or a lumped 10pF load. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load 5.5 4.5 5.5 3.9 4.9 4.7 4.7 5.9 0 4.8 5.6 5.6 6 n/a 8 8 6 6 8 6 8 6 n/a 6 6 6 n/a 6 6 n/a n/a 0.9 n/a 1 1 1 1 1 1 1 1 1 1 1 1 0 n/a 0 0 0 0 0 0 0 0 n/a 0 0 0 n/a 0 0 n/a n/a 0.9 n/a Output Current (mA) I/O H (maximum) I/O L (minimum) Clock Notes
SDRAM Interface
BA0:1 BankSel0:3 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemClkOut0:1 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3[TC0:3] PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr n/a n/a n/a n/a n/a n/a 1.5 n/a n/a 1.5 n/a n/a n/a dc dc 3 3.5 n/a 5 n/a 3.5 4 6.5 3 n/a n/a 5 n/a n/a 3 5 n/a 3 n/a n/a n/a n/a n/a n/a 1 n/a n/a 1 n/a n/a n/a dc dc 1 1 n/a 1 n/a 1 1 1 1 n/a n/a 1 n/a n/a 1 1 n/a 1 19 19 19 40 19 19 19 19 19 19 19 19 12 n/a 12 19 12 12 19 12 19 12 n/a 12 12 12 n/a 19 12 n/a n/a 12 n/a 12 12 12 25 12 12 12 12 12 12 12 12 8 n/a 8 12 8 8 12 8 12 8 n/a 8 8 8 n/a 12 8 n/a n/a 12 n/a SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 1, 2 2 1, 2 2 2 2 2 1, 2 2, 3 2 1, 2 1, 2
External SLAVE Peripheral Interface
External MASTER Peripheral Interface
4
38
PowerPC 405CR Embedded Controller Data Sheet
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest reference clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options:
Strapping Pin Assignments
Function PLL Tuning for 6 M 7 use choice 3 for 7 < M 12 use choice 5 for 12 < M 32 use choice 6 See Note. Option W15 Choice 1; TUNE[5:0] = 010001 Choice 2; TUNE[5:0] = 010010 Choice 3; TUNE[5:0] = 010011 Choice 4; TUNE[5:0] = 010100 Choice 5; TUNE[5:0] = 010101 Choice 6; TUNE[5:0] = 010110 Choice 7; TUNE[5:0] = 010111 Choice 8; TUNE[5:0] = 100100 PLL Forward Divider Bypass mode Divide by 3 Divide by 4 Divide by 6 PLL Feedback Divider Divide by 1 Divide by 2 Divide by 3 Divide by 4 PLB Divider from CPU Divide by 1 Divide by 2 Divide by 3 Divide by 4 OPB Divider from PLB Divide by 1 Divide by 2 Divide by 3 Divide by 4 External Bus Divider from PLB Divide by 2 Divide by 3 Divide by 4 Divide by 5 0 0 0 0 1 1 1 1 C16 0 0 1 1 B16 0 0 1 1 B18 0 0 1 1 T4 0 0 1 1 C17 0 0 1 1 Ball Strapping U13 0 0 1 1 0 0 1 1 B17 0 1 0 1 A14 0 1 0 1 D16 0 1 0 1 U5 0 1 0 1 P18 0 1 0 1 V20 0 1 0 1 0 1 0 1
39
PowerPC 405CR Embedded Controller Data Sheet
Strapping Pin Assignments (Continued)
Function ROM Width 8-bit ROM 16-bit ROM 32-bit ROM Reserved Option Y5 0 0 1 1 Ball Strapping W6 0 1 0 1
Note: The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR, visit the technical documents area of the IBM PowerPC web site.
40
PowerPC 405CR Embedded Controller Data Sheet
Inside of back cover
41
PowerPC 405CR Embedded Controller Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2000
All Rights Reserved Printed in the United States of America August 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: Blue Logic IBM PowerPC 405CR CodePack CoreConnect IBM Logo PowerPC
Other company, product, and service names may be trademarks or service marks of others. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com
SA14-2522-02
42

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